Integrated circuits are typically designed by their manufacturers to have signals occur in specified ranges of voltages and timings. These signal ranges are designed so as to operate and communicate in as wide range of systems and environments as possible. In many cases, during operation multiple signals on interfaces to the integrated circuit are utilized in coordinated signaling or communications where the signals utilized have a fixed timing relationship to each other. One type of integrated circuit that is designed to operate in a broad range of applications are memory devices.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to read-only memory (ROM), which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively. Other types of non-volatile memory include, but are not limited to, Polymer Memory, Ferroelectric Random Access Memory (FeRAM), Ovionics Unified Memory (OUM), and Magnetoresistive Random Access Memory (MRAM).
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that is typically erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks.” The memory cells of a Flash memory array are typically arranged into a “NOR” architecture (each cell directly coupled to a bitline) or a “NAND” architecture (cells coupled into “strings” of cells, such that each cell is coupled indirectly to a bitline and requires activating the other cells of the string for access). Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
In operation, the interface of an integrated circuit or memory device is typically designed to operate in close signal timing relationships to communicate commands and data with the system or communication bus in which it is placed. If the timing relationship of the communication signals and control lines are not maintained, the data or command being communicated may fail or be corrupted. This is particularly the case in modem synchronous memory types which typically have very precise signal timings to allow for high speed data transfers.
Many conditions and environmental conditions can affect the communication environment and actual signal timing experienced by an integrated circuit or memory device operating in a system or communication bus. This includes, but is not limited to, the operating voltage levels, system layout, materials, temperature, and humidity. In particular, the capacitance experienced by an integrated circuit on its interface and control lines in a given system or communication bus can have a strong effect on the actual signal timing.
To deal with these variable signal conditions, as stated above, most integrated circuits and memory devices are designed by their manufacturers with a range of relative signal timings that they can accept. This provides a margin of error to avoid timing violations and allows for real world signal conditions. However, given the increased speed and timing demands of modern high speed memory devices and systems, the effect of real world environment and system conditions on signal timing has increased. Thus, the relative signal timing requirements of a given memory device is increasingly likely to be violated, increasing the likelihood of system errors and loss of data. Further complicating the issue is the fact that not all signals are affected the same, leading to one or more signal lines having more delay for a given memory device and system.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved signal timing adjustment apparatus and methods that can adjust for signal timing variances and allow for operation of integrated circuits and memory devices in a wide range of environments and systems.